US 11,837,307 B2
Managing error-handling flows in memory devices
Kishore Kumar Muchherla, San Jose, CA (US); Shane Nowell, Boise, ID (US); Mustafa N. Kaynak, San Diego, CA (US); Sampath K. Ratnam, San Jose, CA (US); Peter Feeley, Boise, ID (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Devin M. Batutis, San Jose, CA (US); and Xiangang Luo, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 2, 2022, as Appl. No. 17/979,432.
Application 17/979,432 is a continuation of application No. 17/205,091, filed on Mar. 18, 2021, granted, now 11,532,373.
Prior Publication US 2023/0046724 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/42 (2006.01); G11C 16/26 (2006.01); G11C 29/44 (2006.01); G11C 16/10 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 29/12005 (2013.01); G11C 29/44 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
selecting, from a plurality of voltage offset bins, a voltage offset bin associated with a block of the memory device, wherein each voltage offset bin corresponds to a respective predetermined range of threshold voltage offsets to be applied to a base voltage read level during read operations;
performing, on data residing in the block, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on the voltage offset bin associated with the block; and
responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.