US 11,837,303 B2
Optimizing memory access operation parameters
Seungjune Jeon, Santa Clara, CA (US); and Tingjun Xie, Milpitas, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jan. 9, 2023, as Appl. No. 18/094,554.
Application 18/094,554 is a continuation of application No. 17/302,215, filed on Apr. 27, 2021, granted, now 11,557,362.
Prior Publication US 2023/0162810 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/18 (2006.01); G11C 29/44 (2006.01); G11C 29/50 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/18 (2013.01) [G11C 29/12005 (2013.01); G11C 29/44 (2013.01); G11C 29/50004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
writing a predefined data pattern using each value of a plurality of values of a memory access operation parameter;
measuring a corresponding value of a data state metric associated with each value of the plurality of values of the memory access operation parameter; and
selecting, based on the measured values of the data state metric, an optimal value of the memory access operation parameter from the plurality of values of the memory access operation parameter.