US 11,837,288 B2
Memory device
Naoki Matsushita, Seoul (KR)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 9, 2021, as Appl. No. 17/470,867.
Claims priority of application No. 2021-040502 (JP), filed on Mar. 12, 2021.
Prior Publication US 2022/0293176 A1, Sep. 15, 2022
Int. Cl. G11C 11/00 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell including a memory element and a switching element; and
a circuit that applies a first write pulse having a first polarity to the memory cell at the time of writing first data in the memory cell and applies a second write pulse having a second polarity different from the first polarity to the memory cell at the time of writing second data in the memory cell,
wherein
the switching element has polarity dependence according to the first and second polarities.