US 11,837,280 B1
CFET architecture for balancing logic library and SRAM bitcell
Victor Moroz, Saratoga, CA (US); Deepak Sherlekar, Cupertino, CA (US); and Jamil Kawa, Campbell, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Aug. 17, 2020, as Appl. No. 16/995,556.
Claims priority of provisional application 63/027,719, filed on May 20, 2020.
Int. Cl. G11C 11/412 (2006.01); G06F 30/32 (2020.01); H10B 10/00 (2023.01)
CPC G11C 11/412 (2013.01) [G06F 30/32 (2020.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising a digital logic library cell based on complementary-field effect transistor (CFET) architecture, the digital logic library cell comprising:
an n-channel metal-oxide-semiconductor (NMOS) gate-all-around (GAA) channel in a first layer of an electronic structure; and
a p-channel metal-oxide-semiconductor (PMOS) GAA channel in a second layer of the electronic structure,
wherein the PMOS GAA channel is wider compared to the NMOS GAA channel,
wherein the first layer is above the second layer and separated by a dielectric layer,
wherein a space surrounding the NMOS GAA channel is used to access the PMOS GAA channel, and
wherein a parasitic PMOS transistor of the PMOS GAA channel is disposed under an NMOS pass gate of the NMOS GAA channel.