US 11,837,276 B2
Apparatuses and methods for 1T and 2T memory cell architectures
Hiroki Takahashi, Tokyo (JP); and Toru Ishikawa, Kanagawa (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Dec. 14, 2021, as Appl. No. 17/551,095.
Prior Publication US 2023/0186971 A1, Jun. 15, 2023
Int. Cl. G11C 11/4091 (2006.01); G11C 11/406 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 11/406 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a word line coupled to a first memory cell, a second memory cell, and a third memory cell;
a first sense amplifier coupled to the first memory cell;
a second sense amplifier coupled to the second memory cell and the third memory cell; and
a counter circuit coupled to the second sense amplifier, wherein the counter circuit is configured to adjust a count value stored, in part, in the second and the third memory cell based on accesses to the word line.