CPC G11C 11/221 (2013.01) [G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/2293 (2013.01)] | 24 Claims |
1. An apparatus comprising:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias; and
a plurality of capacitors having a first terminal coupled to the storage node via a metal layer, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are planar capacitors that are arranged in a staggered configuration on the metal layer such that a first capacitor of the plurality of capacitors is offset along a horizontal plane diagonally from a second capacitor of the plurality of capacitors.
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