US 11,837,268 B1
Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset
Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); Debo Olaosebikan, San Francisco, CA (US); Tanay Gosavi, Portland, OR (US); Noriyuki Sato, Hillsboro, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/654,560.
Application 17/654,560 is a continuation of application No. 17/653,811, filed on Mar. 7, 2022.
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/221 (2013.01) [G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/2293 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias; and
a plurality of capacitors having a first terminal coupled to the storage node via a metal layer, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are planar capacitors that are arranged in a staggered configuration on the metal layer such that a first capacitor of the plurality of capacitors is offset along a horizontal plane diagonally from a second capacitor of the plurality of capacitors.