| CPC G06F 9/544 (2013.01) [G06F 9/30101 (2013.01); G06F 15/167 (2013.01)] | 8 Claims |
|
1. A data transmission device for in-vehicle multi-core control that includes M (M is an integer of 2 or more) bank memories and N (N is an integer of 2 or more) processors configured to access the M bank memories, the device comprising:
a shared memory on which the M bank memories are arranged and which is accessible by the N processors; and
an access control circuit that controls access to the M bank memories by the N processors based on identification information for specifying the M bank memories, wherein:
the access control circuit:
assigns only one processor used for writing to a bank memory, of the M bank memories, in which writing is performed,
assigns K (K is an integer of 1 or more and N−1 or less) processors used for reading from a bank memory, of the M bank memories, in which reading is performed, and
exclusively controls bank memory access such that the bank memory in which the writing is performed and the bank memory in which the reading is performed are not the same, and
contents of a bank memory in which writing was last performed are copied to the bank memory in which the writing is performed by the only one processor before the access control circuit assigns the only one processor.
|