US 11,836,524 B2
Memory interface for a multi-threaded, self-scheduling reconfigurable computing fabric
Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 19, 2020, as Appl. No. 16/997,180.
Claims priority of provisional application 62/893,584, filed on Aug. 29, 2019.
Prior Publication US 2021/0064435 A1, Mar. 4, 2021
Int. Cl. G06F 9/46 (2006.01); G06F 9/50 (2006.01); G06F 9/448 (2018.01); G06F 9/30 (2018.01); G06F 13/12 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01); G06F 9/54 (2006.01)
CPC G06F 9/5016 (2013.01) [G06F 9/30018 (2013.01); G06F 9/30101 (2013.01); G06F 9/4498 (2018.02); G06F 9/546 (2013.01); G06F 13/128 (2013.01); G06F 13/1673 (2013.01); G06F 13/4239 (2013.01); G06F 13/4243 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A memory interface circuit coupleable to a first interconnection network to transmit a plurality of memory store data request packets to a memory circuit and to receive a plurality of memory load data request packets from the memory circuit, and coupleable to a second, asynchronous packet network for data packet communication with a plurality of configurable circuits to receive a plurality of load requests and a plurality of store requests, the memory interface circuit comprising:
a plurality of registers adapted to store a plurality of tables, the plurality of tables comprising a memory request table, a memory request identifier table, a memory response table, a memory data message table, and a memory response buffer;
a state machine circuit coupled to the plurality of registers, the state machine circuit adapted to receive a load request over the second, asynchronous packet network, and in response to the load request, to obtain a first memory request identifier from the load request, to store the first memory request identifier in the memory request identifier table, to generate one or more memory load request data packets having the memory request identifier for transmission to the memory circuit, and to store load request information in the memory request table; and
a plurality of queues coupled to the state machine circuit, the plurality of queues storing one or more data packets for transmission on the first interconnection network or on the second, asynchronous packet network.