US 11,836,501 B1
System and methods for hardware-based PCIe link up based on post silicon characterization
Ramacharan Sundararaman, San Jose, CA (US); and Nithyananda Miyar, San Jose, CA (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Jan. 18, 2023, as Appl. No. 18/098,388.
Application 18/098,388 is a continuation of application No. 17/325,433, filed on May 20, 2021, granted, now 11,586,446.
Claims priority of provisional application 63/027,910, filed on May 20, 2020.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/4401 (2018.01); G06F 9/445 (2018.01); G06F 9/30 (2018.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 9/4406 (2013.01) [G06F 9/30054 (2013.01); G06F 9/44505 (2013.01); G06F 13/409 (2013.01); G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A hardware-based system, comprising:
a non-volatile storage medium configured to maintain instructions or code set based on post silicon characterization of an electronic device; and
a bootup unit configured to
maintain an initialization sequence in a non-modifiable storage medium wherein, when executed, the initialization sequence is configured to bring a PCIe link up for communication between components in the electronic device;
execute the initialization sequence to read from the non-volatile storage medium the instructions and code set based on the post silicon characterization of the electronic device; and
update at least one attribute of the PCIe link of the electronic device by programming a value associated with at least one attribute of the PCIe link based on the instructions and the code set read from the non-volatile storage medium.