| CPC G06F 9/3806 (2013.01) [G06F 9/30058 (2013.01)] | 25 Claims |
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1. A predictor, comprising:
a memory comprising:
a plurality of entries, wherein each of the plurality of entries comprises a prediction of:
a hash of a next fetch address produced by a fetch block J of a series of successive fetch blocks in program execution order; and
a branch direction produced by the fetch block J; and
an output; and
an input that selects an entry of the plurality of entries for provision on the output;
wherein at least a portion of the output is fed back to the input such that the output provides the prediction of the hash of the next fetch address and the branch direction produced by each fetch block of the series of successive fetch blocks over a series of successive clock cycles; and
wherein the hash of the next fetch address produced by the fetch block J is insufficient for use by an instruction fetch unit to fetch from an instruction cache a fetch block J+1 of the series of successive fetch blocks, whereas the next fetch address produced by the fetch block J is sufficient for use by the instruction fetch unit to fetch from the instruction cache the fetch block J+1.
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