US 11,836,431 B2
Integrated circuit composite test generation
John Lee, San Jose, CA (US); Aveek Sarkar, Palo Alto, CA (US); Altan Odabasi, Canonsburg, PA (US); Scott Johnson, Canonsburg, PA (US); Murat Becer, Canonsburg, PA (US); and William Mullen, Canonsburg, PA (US)
Assigned to ANSYS, INC., Canonsburg, PA (US)
Filed by ANSYS, Inc., Canonsburg, PA (US)
Filed on Jun. 16, 2021, as Appl. No. 17/349,568.
Application 17/349,568 is a continuation of application No. 15/928,744, filed on Mar. 22, 2018, granted, now 11,042,681.
Claims priority of provisional application 62/615,039, filed on Jan. 9, 2018.
Claims priority of provisional application 62/476,347, filed on Mar. 24, 2017.
Prior Publication US 2021/0350059 A1, Nov. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/367 (2020.01)
CPC G06F 30/367 (2020.01) 20 Claims
OG exemplary drawing
 
1. A method for testing a chip package system comprising N processor cores, the method comprising:
receiving a data file characterizing the chip package system, the N processor cores including a first processor core and a second processor core;
applying a first set of switching combinations to the first processor core causing a first number of states and capturing first one or more physical characteristics of behavior of the chip package system in response to the first number of states, wherein the first number of states corresponds to a total number of different states on which the first processor core is tested;
applying a second set of switching combinations to the second processor core;
causing a second number of states and capturing second one or more physical characteristics of the behavior of the chip package system in response to the second number of states, wherein the second number of states corresponds to a total number of different states on which the second processor core is tested; and
combining one or more of the first one or more physical characteristics of the behavior of the chip package system with one or more of the second one or more physical characteristics of the behavior of the chip package system to obtain a composite test.