US 11,836,392 B2
Relocating data to low latency memory
Kishore Kumar Muchherla, Fremont, CA (US); Ashutosh Malshe, Fremont, CA (US); Vamsi Pavan Rayaprolu, San Jose, CA (US); Sampath K. Ratnam, Boise, ID (US); Harish R. Singidi, Fremont, CA (US); and Peter Feeley, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 12, 2021, as Appl. No. 17/450,653.
Application 17/450,653 is a division of application No. 16/175,605, filed on Oct. 30, 2018, granted, now 11,169,747.
Prior Publication US 2022/0027062 A1, Jan. 27, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0673 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0647 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
identifying a plurality of word lines at a first portion of a memory device;
determining a respective error rate for each of the plurality of word lines;
determining that both a first error rate of a first word line of the plurality of word lines and a second error rate of a second word line of the plurality of word lines concurrently satisfy a first threshold condition pertaining to an error rate threshold;
responsive to determining that both the first error rate of the first word line of the plurality of word lines and the second error rate of the second word line of the plurality of word lines concurrently satisfy the first threshold condition pertaining to the error rate threshold, identifying a third word line of the plurality of word lines that is adjacent to the first word line and the second word line; and
relocating, by a processing device, data stored at the third word line to a second portion of the memory device, wherein the second portion of the memory device is associated with a lower read latency than the first portion of the memory device.