US 11,836,377 B2
Data transfer management within a memory device having multiple memory regions with different memory densities
Abdelhakim Alhussien, San Jose, CA (US); Ayberk Ozturk, San Jose, CA (US); Karl D. Schuh, Santa Cruz, CA (US); and Luca Bert, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 30, 2022, as Appl. No. 17/855,579.
Application 17/855,579 is a continuation of application No. 16/948,275, filed on Sep. 10, 2020, granted, now 11,403,032.
Prior Publication US 2022/0334759 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, the processing device configured to perform operations comprising:
determining whether a subset of write units of a primary region of the memory device corresponding to a pre-determined number of write units of the primary region is written with data received from a host system;
determining that at least one write unit in the subset of write units of the primary region stores invalid data; and
in response to determining that the subset of write units of the primary region corresponding to the pre-determined number of write units is written, performing a write operation on at least one write unit of a secondary region of the memory device with respective data of the subset of write units of the primary region, the respective data comprising the invalid data.