CPC G06F 3/0652 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01)] | 23 Claims |
1. A storage system comprising:
a group of multi-level memory cells, each multi-level memory cell comprising multiple pages; and
control circuitry configured to:
receive an indication to selectively erase first data stored on a first page of a first subset of the group of multi-level memory cells, each multi-level memory cell of the first subset of the group of multi-level memory cells comprising the first page and a second page configured to store second data separate from the first data stored on the first page; and
in response to the received indication to selectively erase the first data stored on the first page of the first subset of the group of multi-level memory cells, provide at least one soft erase pulse to the first page of memory cells associated with the first data to induce distribution overlap across different bit levels of the first page of the group of multi-level memory cells to alter a read output of the first data on the first page of memory cells while maintaining a read output of the remaining of the multiple pages of the first subset of the group of multi-level memory cells.
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