US 11,836,354 B2
Distribution of logical-to-physical address entries across multiple memory areas
Jameer Mulani, Bangalore (IN); Kapil Sundrani, Bangalore (IN); and Anindya Rai, Bangalore (IN)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Oct. 4, 2021, as Appl. No. 17/493,722.
Application 17/493,722 is a continuation of application No. 16/824,587, filed on Mar. 19, 2020, granted, now 11,221,771.
Application 16/824,587 is a continuation of application No. 15/641,708, filed on Jul. 5, 2017, granted, now 10,635,331, issued on Apr. 28, 2020.
Prior Publication US 2022/0027063 A1, Jan. 27, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/064 (2013.01); G06F 3/065 (2013.01); G06F 3/0611 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 3/0688 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7201 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for a storage system, comprising:
writing logical-to-physical address entries of an address data structure into one or more memories comprising a first memory area and a second memory area, wherein the second memory area is different from the first memory area;
performing first multiple access requests to a first portion of the one or more memories, wherein the first multiple access requests are directed to one of the first and second memory areas but not both of the first and second memory areas, and wherein consecutively-addressed memory locations of the first portion store non-consecutive logical-to-physical address entries;
performing second multiple access requests to a second portion of the one or more memories, wherein a first one of the second multiple access requests is directed to a first one of the first and second memory areas, wherein a second one of the second multiple access requests is directed to a second one of the first and second memory areas, wherein the second one is different from the first one, and wherein consecutively-addressed memory locations of the second portion store consecutive logical-to-physical address entries;
determining that at least a first number or a first percentage of pairs of consecutive logical-to-physical address entries has a first logical-to-physical address entry stored in a certain one of the first memory area or the second memory area and has a second logical-to-physical address entry stored in another one of the first memory area or the second memory area, wherein the another one is different from the certain one;
when the first number satisfies a predetermined number or the first percentage satisfies a predetermined percentage, writing a first logical-to-physical address entry into a given memory area of the first memory area or the second memory area without determining whether a consecutive logical-to-physical address entry is stored in the same given memory area; and
when the first number fails to satisfy the predetermined number and the first percentage fails to satisfy the predetermined percentage, writing a first logical-to-physical address entry into a particular memory area of the first memory area or the second memory area after determining whether a consecutive logical-to-physical address entry is stored in the same particular memory area,
wherein the second multiple access requests are performed faster than the first multiple access requests.