US 11,836,278 B2
Fault injection event detection at a chip and related systems, method and devices
Michael Klein, Colorado Springs, CO (US)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on May 26, 2021, as Appl. No. 17/303,326.
Claims priority of provisional application 62/704,894, filed on Jun. 2, 2020.
Prior Publication US 2021/0374291 A1, Dec. 2, 2021
Int. Cl. G06F 21/75 (2013.01); H01L 23/00 (2006.01); H03K 3/356 (2006.01)
CPC G06F 21/75 (2013.01) [H01L 23/576 (2013.01); H03K 3/356104 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first fault event detector comprising a first bistable device that changes state in response to a presence of a fault injection event within a first surrounding area of the first fault event detector, wherein the first fault event detector comprises:
an NMOS transistor to selectively pull-down a voltage at a first internal node of the bistable device to a first voltage level utilized to represent a first logic level,
a PMOS transistor to selectively pull-up the voltage at a second internal node of the bistable device to a second voltage level utilized to represent a second logic level,
an inverter having an input coupled with the first internal node and an output coupled with the second internal node; and
a further inverter having an input coupled with the second internal node and an output coupled with the first internal node via a resistive circuit, wherein the resistive circuit to set a responsiveness of the first internal node to changes in voltage level at the output of the further inverter; and
a first vulnerable digital circuit, wherein at least a portion of the first vulnerable digital circuit is located within the first surrounding area.