CPC G06F 21/75 (2013.01) [H01L 23/576 (2013.01); H03K 3/356104 (2013.01)] | 19 Claims |
1. An apparatus, comprising:
a first fault event detector comprising a first bistable device that changes state in response to a presence of a fault injection event within a first surrounding area of the first fault event detector, wherein the first fault event detector comprises:
an NMOS transistor to selectively pull-down a voltage at a first internal node of the bistable device to a first voltage level utilized to represent a first logic level,
a PMOS transistor to selectively pull-up the voltage at a second internal node of the bistable device to a second voltage level utilized to represent a second logic level,
an inverter having an input coupled with the first internal node and an output coupled with the second internal node; and
a further inverter having an input coupled with the second internal node and an output coupled with the first internal node via a resistive circuit, wherein the resistive circuit to set a responsiveness of the first internal node to changes in voltage level at the output of the further inverter; and
a first vulnerable digital circuit, wherein at least a portion of the first vulnerable digital circuit is located within the first surrounding area.
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