US 11,836,277 B2
Secure circuit integrated with memory layer
George Minassian, Santa Clara, CA (US)
Assigned to CROSSBAR, INC., Santa Clara, CA (US)
Filed by CROSSBAR, INC.
Filed on Jun. 22, 2021, as Appl. No. 17/354,634.
Application 17/354,634 is a continuation of application No. 13/673,951, filed on Nov. 9, 2012, granted, now 11,068,620.
Prior Publication US 2021/0342488 A1, Nov. 4, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 21/74 (2013.01)
CPC G06F 21/74 (2013.01) [G06F 2221/2123 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A secure semiconductor chip, comprising:
a logic layer that comprises access logic and a logic circuit formed within the logic layer;
a first memory layer comprising non-volatile resistive memory cells disposed over the logic layer and integrated with the logic layer in a monolithic structure embodying the secure semiconductor chip; and
a plurality of connectors within vias provided between the logic layer and the first memory layer facilitating intra-chip communication within an interior of the secure semiconductor chip; wherein:
the access logic is configured to receive a security key stored in non-volatile resistive memory cells of the first memory layer by way of the plurality of connectors, and
the access logic is configured to provide access to the logic circuit formed within the logic layer in response to successfully receiving the security key.