US 11,836,096 B2
Memory-flow control register
Nikesh Agarwal, Bangalore (IN); Robert Walker, Raleigh, NC (US); and Laurent Isenegger, Morgan Hill, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 22, 2021, as Appl. No. 17/559,320.
Prior Publication US 2023/0195659 A1, Jun. 22, 2023
Int. Cl. G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 9/30 (2018.01)
CPC G06F 13/1668 (2013.01) [G06F 9/30101 (2013.01); G06F 13/1621 (2013.01); G06F 13/1642 (2013.01); G06F 13/4221 (2013.01)] 36 Claims
OG exemplary drawing
 
1. A method comprising:
transmitting, by a controller, a request to read one or more values indicative of a number of memory requests serviceable by a Compute Express Link (CXL) memory device, the one or more values stored in at least one register mapped to a CXL device configuration space of the CXL memory device, the at least one register including one or more of:
a first register that includes at least a first value indicative of a total combined number of write requests and read requests that can be outstanding in or at the CXL memory device;
a second register that includes at least a second value indicative of a number of write requests that can be outstanding in or at the CXL memory device; or
a third register that includes at least a third value indicative of a number of read requests that can be outstanding in or at the CXL memory device; and
receiving, by the controller, a response from the CXL memory device, the response including at least a portion of the one or more values.