US 11,836,085 B2
Cache line coherence state upgrade
Paul J. Moyer, Fort Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Oct. 29, 2021, as Appl. No. 17/514,792.
Prior Publication US 2023/0136114 A1, May 4, 2023
Int. Cl. G06F 12/08 (2016.01); G06F 12/0891 (2016.01); G06F 9/30 (2018.01); G06F 12/0831 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 12/0833 (2013.01)] 48 Claims
OG exemplary drawing
 
1. A method, comprising:
recording an entry indicating that a cache line is exclusive-upgradeable;
removing the cache line from a cache; and
converting a request to insert the cache line into the cache into a request to insert the cache line in the cache in an exclusive state.