CPC G06F 12/0292 (2013.01) [G06F 12/0246 (2013.01); G06F 13/1694 (2013.01); G06F 16/1847 (2019.01); G11C 7/20 (2013.01); G11C 11/40607 (2013.01); G11C 16/20 (2013.01); G11C 16/32 (2013.01); G11C 16/3459 (2013.01); G11C 29/028 (2013.01); G06F 2212/7208 (2013.01); G06F 2212/7209 (2013.01); G11C 2029/4402 (2013.01); G11C 2211/5641 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
an array of memory cells; and
a controller, wherein the controller is coupled to the array of memory cells and includes a field-programmable gate array (FPGA) configured to:
operate the array of memory cells using an initial set of trim settings, wherein the initial set of trim settings are configured to provide operational characteristics for the memory device;
monitor operational characteristics of the array of memory cells; and
determine another set of trim settings for the array of memory cells based on the monitored operational characteristics of the array of memory cells, meta data associated with the data stored in the array of memory cells, and die information associated with the array of memory cells, wherein the determined set of trim settings are configured to change the operational characteristics for the array of memory cells.
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