US 11,836,076 B2
Implementing mapping data structures to minimize sequentially written data accesses
Naveen Bolisetty, Suryapet (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 3, 2023, as Appl. No. 18/105,327.
Application 18/105,327 is a continuation of application No. 17/487,396, filed on Sep. 28, 2021, granted, now 11,615,020.
Claims priority of application No. 202141036475 (IN), filed on Aug. 12, 2021.
Prior Publication US 2023/0185712 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 12/1045 (2016.01); G06F 3/06 (2006.01); G06F 12/1009 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/0246 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0673 (2013.01); G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 12/1054 (2013.01); G06F 2212/65 (2013.01); G06F 2212/68 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A method comprising:
storing, by a processing device on a volatile memory device, logical-to-physical (L2P) mapping data corresponding to sequentially written data;
determining, by the processing device, whether an L2P update criterion is satisfied; and
in response to determining that the L2P update criterion is satisfied, updating, by the processing device, an L2P mapping data structure based on the L2P mapping data, wherein the L2P mapping data structure identifies an initial logical translation unit (LTU) of the sequentially written data and a length of the sequentially written data from the initial LTU.