US 11,836,074 B2
Multiple flash translation layers at a memory device
David A. Palmer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 7, 2020, as Appl. No. 17/065,455.
Prior Publication US 2022/0107886 A1, Apr. 7, 2022
Int. Cl. G06F 12/02 (2006.01); G06F 12/0873 (2016.01); G06F 11/30 (2006.01); G06F 12/1018 (2016.01)
CPC G06F 12/0246 (2013.01) [G06F 11/3037 (2013.01); G06F 12/0873 (2013.01); G06F 12/1018 (2013.01); G06F 2212/7201 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method performed by a memory device, the method comprising:
receiving, at the memory device, data and a command to store the data at the memory device;
selecting, based at least in part on a structure of the data comprising an alignment of the data, a flash translation layer for storing the data, the flash translation layer selected between a first flash translation layer for managing, at least in part, data storage and a first logical to physical (L2P) mapping table and a second flash translation layer for managing, at least in part, a second L2P mapping table and a smaller size of data storage than the first flash translation layer;
determining that a size and the alignment of the data fails to match a size and an alignment of one or more storage locations associated with the first flash translation layer; and
storing, based at least in part on selecting the second flash translation layer, mapping information associated with the data at a subset of storage locations of the second flash translation layer, the mapping information having a format corresponding to the second flash translation layer.