US 11,836,001 B2
Circuit device and real-time clock device
Sho Matsuzaki, Ina (JP)
Assigned to SEIKO EPSON CORPORATION
Filed by Seiko Epson Corporation, Tokyo (JP)
Filed on Jul. 28, 2021, as Appl. No. 17/386,899.
Claims priority of application No. 2020-128473 (JP), filed on Jul. 29, 2020.
Prior Publication US 2022/0035398 A1, Feb. 3, 2022
Int. Cl. G06F 1/14 (2006.01); G11C 7/04 (2006.01); G11C 7/22 (2006.01)
CPC G06F 1/14 (2013.01) [G11C 7/04 (2013.01); G11C 7/222 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A circuit device comprising:
a first power supply line to which a first power supply voltage is supplied;
a second power supply line to which a second power supply voltage is supplied;
a third power supply line;
a power supply circuit that is coupled to the first power supply line and the second power supply line, performs selection of the first power supply voltage or the second power supply voltage, and outputs a third power supply voltage based on the selected power supply voltage to the third power supply line;
a predetermined circuit that is operated by the third power supply voltage;
a first power-on reset circuit that is coupled to the first power supply line and outputs a first power-on reset signal based on the first power supply voltage;
a second power-on reset circuit that is coupled to the third power supply line and outputs a second power-on reset signal in response to the third power supply voltage reaching a lower voltage limit, wherein the first power-on reset outputs the first power-on reset signal in response to the first power supply voltage reaching an upper voltage limit greater than the lower voltage limit; and
a reset control circuit that sets a third power-on reset signal output to at least a part of the predetermined circuit to a reset release level to release the part of the predetermined circuit from a reset state in response to the first power-on reset signal and the second power-on reset signal becoming a reset release level,
wherein the first power-on reset circuit enters a low power consumption mode after the third power-on reset signal becomes a reset release level.