US 11,835,998 B2
System and method for enabling clock stretching during overclocking in response to voltage droop
Amitabh Mehra, Fort Collins, CO (US); Jerry A. Ahrens, Sister Bay, WI (US); Anil Harwani, Austin, TX (US); Richard Martin Born, Fort Collins, CO (US); Dirk J. Robinson, Fort Collins, CO (US); William R. Alverson, Austin, TX (US); and Joshua Taylor Knight, Austin, TX (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 29, 2021, as Appl. No. 17/362,231.
Prior Publication US 2022/0413543 A1, Dec. 29, 2022
Int. Cl. G06F 1/08 (2006.01); G06F 1/28 (2006.01); H03K 5/00 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/28 (2013.01); H03K 5/00006 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method of controlling a clock rate of a processing unit, comprising:
receiving an analog voltage supply to a voltage generator in response to detecting overclocking in the processing unit;
dynamically sensing measurements of an output voltage from the voltage generator based on the received analog voltage supply;
determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements;
determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and
generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.