US 11,835,992 B2
Hybrid memory system interface
Danilo Caraccio, Milan (IT); Marco Dallabora, Melegnano (IT); Daniele Balluchi, Cernusco Sul Naviglio (IT); Paolo Amato, Treviglio (IT); and Luca Porzio, Casalnuovo di Napoli (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 4, 2021, as Appl. No. 17/192,602.
Application 17/192,602 is a continuation of application No. 16/128,882, filed on Sep. 12, 2018, granted, now 10,977,198.
Prior Publication US 2021/0191887 A1, Jun. 24, 2021
Int. Cl. G06F 13/16 (2006.01); G06F 13/28 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 13/28 (2013.01); G06F 2213/28 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A computing system, comprising:
a storage system;
a main memory; and
a processing resource coupled to the storage system via a hybrid interface and to the main memory;
wherein the hybrid interface is configured to, in response to receipt of sub-block sized data requests respectively corresponding to storage I/O requests each having a size not greater than or equal to a host cache line size, prevent the sub-block sized data requests from being aggregated, to a block-sized data request corresponding to a storage I/O request having a size greater than the host cache line size, at the main memory to provide an input/output (I/O) access path via a shared bus, which is coupled to the storage system and supports sub-block level storage I/O access requests and allow the processing resource to directly access the storage system via the hybrid interface.