US 11,835,580 B2
Circuit and method to measure simulation to silicon timing correlation
Ashish Kumar Nayak, San Jose, CA (US); Hugh Thomas Mair, San Jose, CA (US); Anshul Varma, San Jose, CA (US); and Anand Rajagopalan, San Jose, CA (US)
Assigned to MEDIATEK Singapore Pte. Ltd., Singapore (SG)
Filed by MEDIATEK Singapore Pte. Ltd., Singapore (SG)
Filed on Aug. 9, 2021, as Appl. No. 17/397,879.
Claims priority of provisional application 63/119,672, filed on Dec. 1, 2020.
Prior Publication US 2022/0170986 A1, Jun. 2, 2022
Int. Cl. H03K 3/03 (2006.01); G01R 31/3193 (2006.01); H03K 5/134 (2014.01); G01R 31/317 (2006.01); G01R 31/30 (2006.01)
CPC G01R 31/31725 (2013.01) [G01R 31/3016 (2013.01); G01R 31/31937 (2013.01); H03K 3/0315 (2013.01); H03K 5/134 (2014.07)] 9 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
programmable circuitry configured to generate a first oscillator signal in response to a first plurality of control signals and a second oscillator signal in response to a second plurality of control signals having values different from the first plurality of control signals; and
a controller configured to provide the first and second pluralities of control signals to the programmable circuitry, receive the first and second oscillator signals, and determine a central tendency of propagation delay of the programmable circuitry using the first and second oscillator signals.