US 11,818,891 B2
Memory device and fabrication method thereof
Kai Han, Wuhan (CN); Yali Guo, Wuhan (CN); Zhipeng Wu, Wuhan (CN); Lu Zhang, Wuhan (CN); Hang Yin, Wuhan (CN); Simin Liu, Wuhan (CN); and Bo Xu, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed on Jun. 9, 2022, as Appl. No. 17/836,355.
Application 17/836,355 is a continuation of application No. 17/013,044, filed on Sep. 4, 2020, granted, now 11,404,438.
Application 17/013,044 is a continuation of application No. PCT/CN2020/108367, filed on Aug. 11, 2020.
Prior Publication US 2022/0302167 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 29/0649 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a staircase region and an array region, along a first lateral direction;
a wall structure in the staircase region; and
a first separation structure in the array region and arranged along the first lateral direction with the wall structure, wherein:
the wall structure comprises dielectric pairs of a first dielectric layer and a second dielectric layer stacked in the staircase region, and
the first separation structure is vertically through a stack structure in the array region, the stack structure comprising pairs of the first dielectric layer and an electrode layer.