CPC H10B 43/27 (2023.02) [H01L 29/0649 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a staircase region and an array region, along a first lateral direction;
a wall structure in the staircase region; and
a first separation structure in the array region and arranged along the first lateral direction with the wall structure, wherein:
the wall structure comprises dielectric pairs of a first dielectric layer and a second dielectric layer stacked in the staircase region, and
the first separation structure is vertically through a stack structure in the array region, the stack structure comprising pairs of the first dielectric layer and an electrode layer.
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