US 11,818,878 B2
NAND string utilizing floating body memory cell
Benjamin S Louie, Fremont, CA (US); Jin-Woo Han, San Jose, CA (US); and Yuniarto Widjaja, San Jose, CA (US)
Assigned to Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed by Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed on Jul. 19, 2022, as Appl. No. 17/868,722.
Application 15/161,493 is a division of application No. 14/267,112, filed on May 1, 2014, granted, now 9,368,625, issued on Jun. 14, 2016.
Application 17/868,722 is a continuation of application No. 17/219,564, filed on Mar. 31, 2021, granted, now 11,417,658.
Application 17/219,564 is a continuation of application No. 16/706,148, filed on Dec. 6, 2019, granted, now 10,991,697, issued on Apr. 27, 2021.
Application 16/706,148 is a continuation of application No. 16/132,675, filed on Sep. 17, 2018, granted, now 10,546,860, issued on Jan. 28, 2020.
Application 16/132,675 is a continuation of application No. 15/628,931, filed on Jun. 21, 2017, granted, now 10,103,148, issued on Oct. 16, 2018.
Application 15/628,931 is a continuation of application No. 15/161,493, filed on May 23, 2016, granted, now 9,704,578, issued on Jul. 11, 2017.
Claims priority of provisional application 61/829,262, filed on May 31, 2013.
Claims priority of provisional application 61/818,305, filed on May 1, 2013.
Prior Publication US 2022/0367472 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/06 (2006.01); H10B 12/00 (2023.01); H01L 21/265 (2006.01); G11C 16/04 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01); H10B 69/00 (2023.01); H01L 29/78 (2006.01); H01L 23/528 (2006.01); G11C 11/4096 (2006.01); G11C 11/4099 (2006.01); H01L 29/10 (2006.01)
CPC H10B 12/20 (2023.02) [G11C 5/063 (2013.01); G11C 11/4096 (2013.01); G11C 11/4099 (2013.01); G11C 16/0416 (2013.01); G11C 16/0483 (2013.01); H01L 21/26586 (2013.01); H01L 23/528 (2013.01); H01L 27/0886 (2013.01); H01L 29/1087 (2013.01); H01L 29/1095 (2013.01); H01L 29/66659 (2013.01); H01L 29/785 (2013.01); H01L 29/7841 (2013.01); H10B 12/50 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02); H10B 69/00 (2023.02); G11C 2211/4016 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor memory array comprising:
a plurality of NAND string configurations, each said NAND string configuration comprising:
a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;
a select gate drain device connected at one end of said string of semiconductor memory cells, wherein said select gate drain device is not a semiconductor memory cell; and
a select gate source device connected at an opposite end from said one end of said string of semiconductor memory cells, wherein said select gate source device is not a semiconductor memory device;
wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a third region in electrical contact with said floating body region and spaced apart from said first and second regions;
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;
wherein said third region is commonly connected to at least two of said semiconductor memory cells;
wherein each said at least one of said plurality of semiconductor memory cells has only one gate;
wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals;
wherein said select gate drain device is connected to a local bit line; and
at least one transistor isolating said local bit line from a primary bit line.