CPC H03M 13/6577 (2013.01) [G06F 11/1068 (2013.01)] | 20 Claims |
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, the controller configured to:
determine an error correction code (ECC) code length for key value (KV) pair data and/or an ECC code rate for the KV pair data, wherein the ECC code length and the ECC code rate are selected according to a value length of the KV pair data and a correction capability associated with the KV pair data, and wherein the correction capability is based on a detected pattern of the KV pair data;
generate ECC parity based on the selecting; and
program the KV pair data and the generated ECC parity to the memory device.
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