CPC G11C 29/38 (2013.01) [G06F 11/1068 (2013.01); G11C 11/4087 (2013.01); G11C 11/40618 (2013.01); G11C 29/36 (2013.01); G11C 2029/3602 (2013.01)] | 35 Claims |
1. An integrated circuit that comprises:
a memory unit comprising memory cells, an output port, and read circuitry; and
a processing unit;
wherein the read circuitry comprises a reduction unit and a first group of in-memory read paths for outputting up to a first number of bits through the output port;
wherein the processing unit is configured to send to the memory unit a read request for reading a second number of bits from the memory unit; and
wherein the reduction unit is configured to control the in-memory read paths, during a read operation triggered by the read request, based on the first number of bits and the second number of bits, wherein the reduction unit is configured to utilize portions of relevant in-memory read paths during the read operation and to maintain in a low power mode a sense amplifier of at least some irrelevant in-memory read paths.
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