CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] | 18 Claims |
1. A storage device, comprising:
a non-volatile memory including a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines, wherein the control circuitry is configured to program the memory cells of the plurality of word lines in a plurality of programming loops, the programming loops including:
applying a programming pulse to a selected word line of the plurality of word lines;
applying a verify pulse VN to the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells being programmed to a data state N−1, wherein the data state N−1 corresponds to a data state having a threshold voltage range lower than a threshold voltage range corresponding to the data state N; and
inhibiting further programming of the memory cells already having been programmed to data state N in response to the verify of the lower tail of data state N passing, and to incrementally advance the data states being verified by incrementing N to N+1 (N=N+1).
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