US 11,817,153 B2
Memory device that performs erase operation to preserve data reliability
Jinyoung Kim, Seoul (KR); Sehwan Park, Yongin-si (KR); Ilhan Park, Suwon-si (KR); Youngdeok Seo, Seoul (KR); and Dongmin Shin, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 15, 2021, as Appl. No. 17/503,197.
Claims priority of application No. 10-2020-0181181 (KR), filed on Dec. 22, 2020.
Prior Publication US 2022/0199164 A1, Jun. 23, 2022
Int. Cl. G11C 16/16 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory block comprising a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and vertically stacked; and
a control circuit configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks,
wherein the memory block further comprises:
a first erase transistor directly connected to the common source line, and configured to apply the erase voltage to the common source line; and
a second erase transistor directly connected to the plurality of bit lines, and configured to apply the erase voltage to the plurality of bit lines.