CPC G09G 3/3225 (2013.01) [G09G 2310/0243 (2013.01); G09G 2310/0278 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01); G09G 2330/021 (2013.01)] | 20 Claims |
1. A host processor comprising:
a clock source configured to generate a clock signal that swings periodically between a high level and a low level;
a video mode controller configured to generate a first synchronization signal based on the clock signal, and generate a wakeup interrupt by measuring a frame update period of a display panel controlled by a display driver integrated circuit; and
a display controller configured to generate frame data based on the first synchronization signal by enabling an image providing path based on the wakeup interrupt,
wherein the host processor is configured to output the first synchronization signal to the display driver integrated circuit, and output the frame data for every frame update period to the display driver integrated circuit, and
wherein the display driver integrated circuit is configured to control the display panel such that a frame image corresponding to the frame data is displayed on the display panel based on the first synchronization signal without storing the frame data.
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