US 11,816,354 B2
Persistent memory adaptation
Owen Martin, Hopedale, MA (US); Dustin Zentz, Northborough, MA (US); and Vladimir Desyatov, Hollis, NH (US)
Assigned to EMC IP Holding Company LLC, Hopkinton, MA (US)
Filed by EMC IP Holding Company LLC, Hopkinton, MA (US)
Filed on Jul. 27, 2020, as Appl. No. 16/939,146.
Prior Publication US 2022/0027087 A1, Jan. 27, 2022
Int. Cl. G06F 3/06 (2006.01); G06N 20/00 (2019.01)
CPC G06F 3/0659 (2013.01) [G06F 3/064 (2013.01); G06F 3/0611 (2013.01); G06F 3/0653 (2013.01); G06F 3/0689 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising a memory and at least one processor configured to:
analyze an input/output (IO) workload of a storage array;
in a backend portion of the storage array:
establish at least one logical drive corresponding to one or more address spaces within a persistent data storage device of the storage array, wherein the address spaces correspond to a physical location within the persistent data storage device;
identify each address space with a write request density above a threshold;
allocate a persistent memory region (PMR) of persistent cache memory within the persistent data storage device to cache write data requests targeting the address spaces with the write request densities above the threshold;
establish a virtualized memory storage corresponding to a persistent memory region (PMR) of persistent cache memory within the persistent data storage device; and
direct IO write requests to the at least one logical drive or the virtualized memory storage based on the identified address spaces with write request densities above the threshold.