US 11,816,039 B2
Multi-mode protected memory
Adrian Pearson, Hillsboro, OR (US); Bing Zhu, Shanghai (CN); Elena Agranovsky, Jerusalem (IL); Tomas Winkler, Mevasert Zion (IL); and Yang Huang, Shanghai (CN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/441,214
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Apr. 19, 2019, PCT No. PCT/CN2019/083388
§ 371(c)(1), (2) Date Sep. 20, 2021,
PCT Pub. No. WO2020/211070, PCT Pub. Date Oct. 22, 2020.
Prior Publication US 2022/0164293 A1, May 26, 2022
Int. Cl. G06F 12/14 (2006.01)
CPC G06F 12/1408 (2013.01) [G06F 12/1425 (2013.01); G06F 12/1466 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a protected memory; and
a protected memory controller to include circuitry configured to:
control access to the protected memory in a selected mode to include a transient mode and a permanent mode;
authenticate memory operations directed to the protected memory based on a re-programmable authentication key in the transient mode or based on a one-time programmable authentication key in the permanent mode;
maintain a resettable write counter value to indicate a count of write operations to the protected memory in the transient mode; and
maintain a non-resettable write counter value to indicate a count of write operations to the protected memory in the permanent mode.