US 11,816,008 B2
Post code reporting via secure digital memory interface
Yanbai Wang, Shanghai (CN); and Lingjing Zeng, Shanghai (CN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/056,398
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 24, 2018, PCT No. PCT/CN2018/123146
§ 371(c)(1), (2) Date Nov. 17, 2020,
PCT Pub. No. WO2020/132821, PCT Pub. Date Jul. 2, 2020.
Prior Publication US 2021/0263816 A1, Aug. 26, 2021
Int. Cl. G06F 11/00 (2006.01); G06F 11/22 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/2284 (2013.01) [G06F 13/1668 (2013.01); G06F 13/4282 (2013.01)] 15 Claims
OG exemplary drawing
 
1. At least one non-transitory machine readable medium including instructions that, when executed by a first device, cause the first device to perform operations for reporting power-on self-test (POST) codes of a personal computing device via a secure digital (SD) interface, comprising:
following reception of system power, assigning a first signal connection and a second signal connection of a plurality of signal connections of said SD interface for conveyance of a general purpose input signal and conveyance of a general purpose output signal;
writing, to said first signal connection, a first write signal having a first write logic state;
reading, from said second signal connection, a first read signal having a first read logic state;
writing, to said first signal connection, a second write signal having a second write logic state;
reading, from said second signal connection, a second read signal having a second read logic state; and
responsive to a reading of said first read signal having said first read logic state equal to said first write logic state, followed by a reading of said second read signal having said second read logic state equal to said second write logic state, initiating a serial data signal to at least one of said first and second signal connections.