US 11,812,616 B2
Trench gate high voltage transistor for embedded memory
Wei Cheng Wu, Zhubei (TW); Alexander Kalnitsky, San Francisco, CA (US); and Chien-Hung Chang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Nov. 23, 2021, as Appl. No. 17/533,339.
Application 17/533,339 is a continuation of application No. 16/404,983, filed on May 7, 2019, granted, now 11,189,628.
Claims priority of provisional application 62/689,893, filed on Jun. 26, 2018.
Prior Publication US 2022/0085041 A1, Mar. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/35 (2023.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 21/033 (2006.01); H01L 29/06 (2006.01); H10B 43/50 (2023.01)
CPC H10B 43/35 (2023.02) [H01L 21/0337 (2013.01); H01L 29/0649 (2013.01); H01L 29/40117 (2019.08); H01L 29/42352 (2013.01); H10B 43/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric, the first logic gate dielectric being disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode being disposed conformally along the first logic gate dielectric within the logic device trench; and
a hard mask layer disposed on the first logic gate electrode within the logic device trench,
wherein the hard mask layer has a top surface coplanar with that of the first logic gate electrode.