US 11,812,556 B2
Printed circuit board and manufacturing method thereof
Jung Hyun Park, Suwon-si (KR); Yong Ho Baek, Suwon-si (KR); and Jae Hoon Choi, Suwon-si (KR)
Assigned to Samsung Electro-Mechanics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electro-Mechanics Co., Ltd., Suwon-si (KR)
Filed on Jul. 13, 2021, as Appl. No. 17/374,409.
Application 17/374,409 is a continuation of application No. 16/812,640, filed on Mar. 9, 2020, granted, now 11,096,286.
Application 16/812,640 is a continuation of application No. 16/033,427, filed on Jul. 12, 2018, granted, now 10,674,608, issued on Jun. 2, 2020.
Application 16/033,427 is a continuation of application No. 14/794,632, filed on Jul. 8, 2015, granted, now 10,076,038, issued on Sep. 11, 2018.
Claims priority of application No. 10-2014-0103893 (KR), filed on Aug. 11, 2014.
Prior Publication US 2021/0345491 A1, Nov. 4, 2021
Int. Cl. H05K 1/18 (2006.01); H05K 3/46 (2006.01)
CPC H05K 1/185 (2013.01) [H05K 3/4682 (2013.01); H05K 2201/0195 (2013.01); H05K 2203/1469 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A printed circuit board comprising:
a first insulating layer;
a first circuit pattern, disposed on one surface of the first insulating layer, enclosed in the first insulating layer in such a way that one surface of the first circuit pattern is exposed through the one surface of the first insulating layer and remaining surfaces of the first circuit pattern excluding the one surface of the first circuit pattern are covered by the first insulating layer;
a second circuit pattern, disposed on second surface of the first insulating layer, spaced apart from the first circuit pattern and protruded from the second surface of the first insulating layer toward an opposite side of the first circuit pattern;
an adhesive layer disposed on the second surface of the first insulating layer to contact a portion of the first insulating layer and a side surface of the second circuit pattern;
an electronic component disposed on the adhesive layer and adjacent to the second circuit pattern such that the electronic component at least partially overlaps the second circuit pattern along a direction normal to a thickness direction of the printed circuit board;
a second insulating layer disposed on the second surface of the first insulating layer and covering at least a portion of each of the electronic component and the second circuit pattern;
a first via formed in the first insulating layer and connecting the second circuit pattern to the first circuit pattern;
a second via formed in the second insulating layer and connecting the second circuit pattern to a third circuit pattern disposed on one surface of the second insulating layer;
and a third via formed in the first insulating layer and connected to the electronic component,
wherein a height of the second via is greater than a height of the first via,
wherein the first via and the second via have shapes tapered in same directions to each other, and
wherein the second via and the third via have shapes tapered in opposite directions to each other.