US 11,812,045 B2
Decoder and decoding method
Takahiro Nishi, Nara (JP); Tadamasa Toma, Osaka (JP); Kiyofumi Abe, Osaka (JP); and Yusuke Kato, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Jun. 7, 2022, as Appl. No. 17/833,986.
Application 17/833,986 is a continuation of application No. 17/241,670, filed on Apr. 27, 2021, granted, now 11,388,429.
Application 17/241,670 is a continuation of application No. PCT/JP2019/047886, filed on Dec. 6, 2019.
Claims priority of provisional application 62/839,033, filed on Apr. 26, 2019.
Claims priority of provisional application 62/808,540, filed on Feb. 21, 2019.
Claims priority of provisional application 62/776,792, filed on Dec. 7, 2018.
Claims priority of provisional application 62/776,780, filed on Dec. 7, 2018.
Prior Publication US 2022/0312025 A1, Sep. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 19/44 (2014.01); H04N 19/119 (2014.01); H04N 19/176 (2014.01); H04N 19/70 (2014.01)
CPC H04N 19/44 (2014.11) [H04N 19/119 (2014.11); H04N 19/176 (2014.11); H04N 19/70 (2014.11)] 3 Claims
OG exemplary drawing
 
1. A decoder that decodes an image, the decoder comprising:
circuitry; and
memory coupled to the circuitry, wherein
in operation, the circuitry:
splits a current picture to be decoded into two or more tiles; and
decodes the current picture by performing the decoding on a slice, the slice being rectangular-shaped, the slice being made up of one or more tiles or a part of a tile obtained by the splitting,
in the decoding of the current picture, the circuitry derives first information on a region in a predetermined manner without retrieving the first information from header information, the region being occupied by a slice located at a lower-right corner of the current picture, and
the first information is not included in the header information.