| CPC H04L 43/106 (2013.01) [H04L 69/18 (2013.01); H04L 69/28 (2013.01)] | 22 Claims |
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1. A network device comprising:
a packet processor operable to process network packets according to a plurality of network protocols;
a memory programmed with a plurality of instruction sets associated with a plurality of timestamp formats corresponding to the plurality of network protocols; and
a timestamp generator including a plurality of timestamp compute circuits, each timestamp compute circuit including:
an arithmetic logic unit (ALU); and
an operand selector circuit operable to select operands for the ALU from one or more configurable parameters, a base timestamp input, and one or more intermediate results,
wherein each timestamp compute circuit is operable to execute an instruction set selected from the plurality of instruction sets stored in the memory to generate a formatted timestamp according to a network protocol of a network packet being processed by the packet processor, and
wherein the plurality of timestamp compute circuits is operable to generate formatted timestamps in a pipelined manner to keep up a packet rate.
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