| US 11,811,479 B2 | ||
| Integrated circuit | ||
| Yutaka Murakami, Kanagawa (JP); Tomohiro Kimura, Osaka (JP); and Mikihiro Ouchi, Osaka (JP) | ||
| Assigned to Panasonic Intellectual Property Corporation of America, Torrance, CA (US) | ||
| Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US) | ||
| Filed on Dec. 13, 2022, as Appl. No. 18/065,533. | ||
| Application 18/065,533 is a continuation of application No. 17/171,812, filed on Feb. 9, 2021, granted, now 11,563,476, issued on Jan. 24, 2023. | ||
| Application 17/171,812 is a continuation of application No. 16/773,204, filed on Jan. 27, 2020, granted, now 10,951,294, issued on Mar. 16, 2021. | ||
| Application 16/773,204 is a continuation of application No. 16/421,198, filed on May 23, 2019, granted, now 10,587,327, issued on Mar. 10, 2020. | ||
| Application 16/421,198 is a continuation of application No. 16/203,249, filed on Nov. 28, 2018, granted, now 10,355,765, issued on Jul. 16, 2019. | ||
| Application 16/203,249 is a continuation of application No. PCT/JP2017/022622, filed on Jun. 20, 2017. | ||
| Claims priority of application No. 2016-140331 (JP), filed on Jul. 15, 2016; application No. 2017-000512 (JP), filed on Jan. 5, 2017; application No. 2017-040865 (JP), filed on Mar. 3, 2017; and application No. 2017-107012 (JP), filed on May 30, 2017. | ||
| Prior Publication US 2023/0147488 A1, May 11, 2023 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H04B 7/06 (2006.01); H04B 7/0452 (2017.01); H04L 1/06 (2006.01); H04L 1/00 (2006.01); H04B 7/0456 (2017.01); H04L 27/26 (2006.01); H04B 1/707 (2011.01); H04L 27/00 (2006.01) | ||
| CPC H04B 7/0682 (2013.01) [H04B 7/0452 (2013.01); H04B 7/0456 (2013.01); H04B 7/0697 (2013.01); H04L 1/0003 (2013.01); H04L 1/0618 (2013.01); H04B 1/707 (2013.01); H04B 7/0602 (2013.01); H04B 2201/70703 (2013.01); H04L 27/0008 (2013.01); H04L 27/2602 (2013.01); H04L 27/2626 (2013.01); Y02D 30/70 (2020.08)] | 7 Claims |
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1. An integrated circuit comprising:
at least one input which, in operation, receives an input; and control circuity, which is coupled to the at least one input and which, in operation, controls:
receiving a first precoded signal and a second precoded signal; and
performing a decoding and demodulation process on the first precoded signal and the second precoded signal, wherein
in response to only one of the first precoded signal and the second precoded signal having its phase changed through precoding by a communication partner apparatus, the decoding and demodulation process generates one layer of signal and performs demodulation with phase change on the one layer of signal, and in response to both of the first precoded signal and the second precoded signal having their phase changed through precoding by the communication partner apparatus, the decoding and demodulation process generates two layers of signals and performs demodulation without phase change on the two layers of signals. |