CPC H03K 19/1774 (2013.01) [G06N 3/063 (2013.01); H03K 19/17748 (2013.01)] | 20 Claims |
1. A method for operating an integrated circuit chip comprising multiple tiles, the method comprising:
determining a configuration for the tiles of the integrated circuit for execution of a computation;
when the configuration for the tiles satisfies a first criterion, operating the integrated circuit in a first mode, including:
concurrently receiving respective input data for the computation at each of the tiles of the integrated circuit; and
when the configuration for the tiles satisfies a second criterion, operating the integrated circuit in a second mode, including:
at a first time, concurrently receiving respective first input data for the computation at each tile of a first group of tiles of the integrated circuit;
at the first time, storing respective second input data for the computation in each of multiple delay registers, each delay register corresponding to a tile of a second group of tiles of the integrated circuit; and
at a second time, releasing the second input data from the delay registers and receiving the released respective second input data at each tile of the second group of tiles.
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