US 11,811,401 B2
Dual-mode operation of application specific integrated circuits
Reiner Pope, Mountain View, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Appl. No. 17/634,744
Filed by Google LLC, Mountain View, CA (US)
PCT Filed Aug. 14, 2020, PCT No. PCT/US2020/046287
§ 371(c)(1), (2) Date Feb. 11, 2022,
PCT Pub. No. WO2021/030653, PCT Pub. Date Feb. 18, 2021.
Claims priority of provisional application 62/886,481, filed on Aug. 14, 2019.
Prior Publication US 2022/0286135 A1, Sep. 8, 2022
Int. Cl. H03K 19/17736 (2020.01); G06N 3/063 (2023.01); H03K 19/17748 (2020.01)
CPC H03K 19/1774 (2013.01) [G06N 3/063 (2013.01); H03K 19/17748 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for operating an integrated circuit chip comprising multiple tiles, the method comprising:
determining a configuration for the tiles of the integrated circuit for execution of a computation;
when the configuration for the tiles satisfies a first criterion, operating the integrated circuit in a first mode, including:
concurrently receiving respective input data for the computation at each of the tiles of the integrated circuit; and
when the configuration for the tiles satisfies a second criterion, operating the integrated circuit in a second mode, including:
at a first time, concurrently receiving respective first input data for the computation at each tile of a first group of tiles of the integrated circuit;
at the first time, storing respective second input data for the computation in each of multiple delay registers, each delay register corresponding to a tile of a second group of tiles of the integrated circuit; and
at a second time, releasing the second input data from the delay registers and receiving the released respective second input data at each tile of the second group of tiles.