CPC H01L 29/78696 (2013.01) [H01L 21/823807 (2013.01); H01L 21/823857 (2013.01); H01L 27/092 (2013.01); H01L 29/42392 (2013.01); H01L 29/775 (2013.01)] | 20 Claims |
1. An integrated circuit, comprising:
a substrate;
first and second n-type wells and a p-type well over the substrate, wherein the first and the second n-type wells sandwich the p-type well from a top view;
a first row of cells over the p-type well and the first n-type well from a top view, wherein the first row of cells include gate-all-around (GAA) nanosheet (NS) cells mixed with GAA nanowire (NW) cells; and
a second row of cells over the p-type well and the second n-type well from a top view, wherein the second row of cells include GAA NS cells mixed with GAA NW cells, wherein each GAA NS cell includes an NMOS GAA NS transistor and a PMOS GAA NS transistor, each GAA NW cell includes an NMOS GAA NW transistor and a PMOS GAA NW transistor,
wherein in a cross-sectional view, each of the GAA NS and NW transistors includes vertically stacked multiple first channels, a first gate dielectric layer wrapping around the first channels, and a first gate electrode wrapping around the first gate dielectric layer, wherein the first channels of the GAA NS transistors are wider than the first channels of the GAA NW transistors.
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