US 11,810,980 B2
Channel formation for three dimensional transistors
Chieh-Jen Ku, Hillsboro, OR (US); Pei-Hua Wang, Beaverton, OR (US); Bernhard Sell, Portland, OR (US); Martin M. Mitan, Beaverton, OR (US); and Leonard C. Pipes, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 28, 2019, as Appl. No. 16/457,621.
Prior Publication US 2020/0411697 A1, Dec. 31, 2020
Int. Cl. H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 27/06 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 21/76829 (2013.01); H01L 27/0688 (2013.01); H01L 27/1259 (2013.01); H01L 29/6675 (2013.01); H01L 29/78618 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a transistor above the substrate, wherein the transistor includes a channel layer above the substrate, and wherein the channel layer includes:
a first channel material of a first conductivity;
elements of one or more additional materials distributed within the channel layer, wherein the channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity;
a capping layer on the first channel material; and
a spacer on the capping layer, the spacer and the capping layer having a same lateral width.