US 11,810,971 B2
Integrated design for III-Nitride devices
Yifeng Wu, Goleta, CA (US); and John Kirk Gritters, Santa Barbara, CA (US)
Assigned to Transphorm Technology, Inc., Goleta, CA (US)
Appl. No. 17/047,602
Filed by Transphorm Technology, Inc., Goleta, CA (US)
PCT Filed Mar. 20, 2020, PCT No. PCT/US2020/024015
§ 371(c)(1), (2) Date Oct. 14, 2020,
PCT Pub. No. WO2020/191357, PCT Pub. Date Sep. 24, 2020.
Claims priority of provisional application 62/821,946, filed on Mar. 21, 2019.
Prior Publication US 2021/0408273 A1, Dec. 30, 2021
Int. Cl. H01L 29/778 (2006.01); H01L 23/48 (2006.01); H01L 29/20 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 23/481 (2013.01); H01L 29/2003 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a III-N device comprising a conductive substrate on a first side of a III-N material structure that includes an electrically insulating buffer layer, and a first gate, a first source, and a first drain over a second side of the III-N material structure opposite the substrate, wherein the first source is electrically separated from the conductive substrate by the electrically insulating buffer layer;
a field effect transistor (FET) comprising a second semiconductor material structure, and second gate, a second source, and a second drain, the second source and the second gate being over an opposite side of the second semiconductor material structure from the second drain, wherein the second drain of the FET is physically mounted and electrically connected to a source pad of the first source of the III-N device; and
a via-hole extending through a portion of the III-N material structure and terminating at the conductive substrate, wherein the first gate is electrically connected to the conductive substrate by a metal layer formed in the via-hole.