US 11,810,964 B2
Semiconductor devices including gate spacer
Bongseok Suh, Seoul (KR); Daewon Kim, Hwaseong-si (KR); Beomjin Park, Hwaseong-si (KR); Sukhyung Park, Seoul (KR); Sungil Park, Suwon-si (KR); Jaehoon Shin, Suwon-si (KR); Bongseob Yang, Suwon-si (KR); Junggun You, Ansan-si (KR); and Jaeyun Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 1, 2020, as Appl. No. 17/060,193.
Claims priority of application No. 10-2020-0042140 (KR), filed on Apr. 7, 2020.
Prior Publication US 2021/0313442 A1, Oct. 7, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/772 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 29/6656 (2013.01) [H01L 29/1033 (2013.01); H01L 29/42376 (2013.01); H01L 29/66553 (2013.01); H01L 29/78696 (2013.01); H01L 21/28141 (2013.01); H01L 21/823468 (2013.01); H01L 29/1037 (2013.01); H01L 29/66719 (2013.01); H01L 29/7727 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first active region defined on a substrate;
a first gate electrode across the first active region;
a first drain region in the first active region at a position adjacent to the first gate electrode;
an undercut region between the first active region and a metal portion of the first gate electrode;
a first gate spacer on a side surface of the first gate electrode and protruding into the undercut region, wherein the first gate spacer includes
an upper portion on the side surface of the first gate electrode, and
a lower portion extending from the upper portion into the undercut region,
wherein the first active region comprises a plurality of channel regions, each of the plurality of channel regions being in contact with the first drain region, and
wherein the first gate electrode surrounds a top surface, a side surface, and a bottom surface of at least one of the plurality of channel regions; and
a first gate dielectric layer between the first gate electrode and the plurality of channel regions and extending between the first gate electrode and the first gate spacer, the first gate dielectric layer being in contact with a side surface and a top surface of the lower portion,
wherein the undercut region is between the metal portion of the first gate electrode and an uppermost channel region of the plurality of channel regions.