US 11,810,963 B2
Gate spacer structure of FinFET device
Chung-Ting Li, Hsinchu (TW); Bi-Fen Wu, Taichung (TW); Jen-Hsiang Lu, Taipei (TW); and Chih-Hao Chang, Chu-Bei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 24, 2021, as Appl. No. 17/328,046.
Application 16/419,292 is a division of application No. 15/726,074, filed on Oct. 5, 2017, granted, now 10,319,832, issued on Jun. 11, 2019.
Application 17/328,046 is a continuation of application No. 17/011,265, filed on Sep. 3, 2020, granted, now 11,018,242.
Application 17/011,265 is a continuation of application No. 16/725,526, filed on Dec. 23, 2019, granted, now 10,811,517, issued on Oct. 20, 2020.
Application 16/725,526 is a continuation of application No. 16/419,292, filed on May 22, 2019, granted, now 10,522,653, issued on Dec. 31, 2019.
Claims priority of provisional application 62/491,716, filed on Apr. 28, 2017.
Prior Publication US 2021/0288162 A1, Sep. 16, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/2815 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/41791 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/6681 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/823468 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a semiconductor fin over a substrate;
a first gate stack overlapping with the semiconductor fin in a plan view;
a first epitaxial source/drain region adjacent to the first gate stack and extending into the semiconductor fin;
a first spacer structure laterally interposed between a sidewall of the first gate stack and the first epitaxial source/drain region, the first spacer structure comprising:
a first L-shaped spacer along the sidewall of the first gate stack; and
a second spacer along an outer sidewall of a vertical portion of the first L-shaped spacer, a lateral portion of the first L-shaped spacer extending from an outer sidewall of the second spacer to the first epitaxial source/drain region; and
a conductive feature adjacent the first gate stack and in physical contact with a top surface of the first epitaxial source/drain region, a sidewall of the conductive feature being laterally spaced apart from the outer sidewall of the second spacer by a first distance of between about 10 nm and about 25 nm, the sidewall of the conductive feature facing the outer sidewall of the second spacer.