	US 11,810,959 B2
	Transistor layout to reduce kink effect
Meng-Han Lin, Hsinchu (TW); Te-Hsin Chiu, Miaoli County (TW); and Wei Cheng Wu, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 1, 2022, as Appl. No. 17/829,542.
Application 17/829,542 is a continuation of application No. 17/218,307, filed on Mar. 31, 2021.
Application 17/218,307 is a continuation of application No. 16/661,108, filed on Oct. 23, 2019, granted, now 10,971,590, issued on Apr. 6, 2021.
Application 16/661,108 is a continuation of application No. 15/989,606, filed on May 25, 2018, granted, now 10,510,855, issued on Dec. 17, 2019.
Claims priority of provisional application 62/585,636, filed on Nov. 14, 2017.
Prior Publication US 2022/0293758 A1, Sep. 15, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/00 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)

CPC H01L 29/42376 (2013.01) [H01L 21/28123 (2013.01); H01L 21/76224 (2013.01); H01L 29/0692 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/4238 (2013.01); H01L 29/6659 (2013.01); H01L 29/66598 (2013.01); H01L 29/7833 (2013.01); H01L 29/7834 (2013.01); H01L 29/665 (2013.01)]

20 Claims

1. An integrated chip, comprising:

a substrate;

an isolation structure arranged within the substrate and surrounding an upper surface of the substrate, wherein the isolation structure comprises one or more surfaces forming one or more trenches along opposing sides of the upper surface of the substrate; and

a conductive gate over the substrate and laterally between a source region and a drain region disposed within the upper surface of the substrate, wherein the conductive gate is disposed within the one or more trenches and continuously extends in opposing directions past the one or more trenches.