US 11,810,949 B2
Semiconductor arrangement and method of making
Shih-Wei Peng, Hsinchu (TW); and Jiann-Tyng Tzeng, Hsin Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on Jun. 2, 2021, as Appl. No. 17/336,469.
Claims priority of provisional application 63/163,494, filed on Mar. 19, 2021.
Prior Publication US 2022/0302255 A1, Sep. 22, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 29/7827 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor arrangement, comprising:
a first source pad formed over a semiconductor layer;
a first nanosheet contacting the first source pad;
a gate pad adjacent the first nanosheet;
a first drain pad over the gate pad and contacting the first nanosheet;
a backside interconnect line under the gate pad and the first source pad; and
a backside gate contact contacting the backside interconnect line and the gate pad.