US 11,810,948 B2
Semiconductor device and method
Hsin-Yi Lee, Hsinchu (TW); Cheng-Lung Hung, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 11, 2021, as Appl. No. 17/317,519.
Claims priority of provisional application 63/158,987, filed on Mar. 10, 2021.
Prior Publication US 2022/0293731 A1, Sep. 15, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 27/092 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
nanostructures on a substrate, the nanostructures comprising a channel region;
a gate dielectric layer wrapping around each of the nanostructures;
a first work function tuning layer on the gate dielectric layer, the first work function tuning layer comprising a first n-type work function metal, aluminum, and carbon, the first n-type work function metal comprising zirconium, hafnium, or niobium;
a glue layer on the first work function tuning layer; and
a fill layer on the glue layer.